A method is known from the prior art for transferring a useful layer 3 onto a carrier substrate 4, shown in FIG. 1, this method comprising the following main steps:
in a step a), the formation of an embrittlement plane 2 by implantation of light species into a first substrate 1 in such a manner as to define the boundaries of a useful layer 3 between the plane and a surface of the first substrate 1;
in a step b), the application of the carrier substrate 4 onto the surface of the first substrate 1 in order to form an assembly to be fractured 5;
in a step c), the thermal embrittlement treatment of the assembly to be fractured 5;
in a step d), the initiation and propagation of a fracture wave within the first substrate 1 along the embrittlement plane 2.
During this process, the implanted species lead to the development of microcavities. The thermal embrittlement treatment has the effect of promoting the growth, the coalescence and applying pressure to these microcavities. Under the effect of this thermal treatment alone, or by means of additional external forces, the initiation and the self-sustaining propagation of a fracture wave allows the useful layer 3 to be transferred by detachment in the embrittlement plane 2.
This method, notably described in the International Publications WO 2005/043615 and WO 2005/043616 and denoted by the term “SMART CUT®,” is, in particular, useful for the fabrication of silicon-on-insulator substrates. In this case, the first substrate 1 and the carrier substrate 4 consist of silicon wafers, and one and/or the other of the first substrate 1 and of the carrier substrate 4 undergo surface oxidation.
The silicon-on-insulator substrates 1, 4 must comply with very precise specifications. This is particularly the case for the mean thickness and the thickness uniformity of the useful layer 3. Compliance with these specifications is required for the correct operation of the semiconductor devices that will be formed within and on this useful layer 3.
In some cases, the architecture of these semiconductor devices requires the availability of silicon-on-insulator substrates having a useful layer 3 with a very small mean thickness, for example, less than 50 nm, or even less than 10 nm, and a very constant thickness uniformity on the surface of the substrate. The expected thickness uniformity may thus be of the order of 1% at the most, corresponding to variation maxima typically going from +/−0.1 nm to +/−1 nm over the whole surface of the substrate.
It is usual, following the “SMART CUT®” method, to apply complementary steps for finishing the useful layer 3, such as etches or thermal treatments for surface smoothing, in order to try to achieve the desired specification level.
The thickness of the useful layer 3 is not perfectly uniform after the fracture step. These thickness variations may, for example, take the form of a periodic pattern whose amplitude is of the order of a nm or of half a nanometer and whose wavelength is of the order of a mm, or up to a cm. The periodic pattern may be apparent over the entirety of the useful layer 3, or only over a part. Variations in thickness may also appear within a given region of the useful layer 3, generally referred to as a “dense region,” corresponding to the region of initiation of the fracture wave. The thickness variations may also arise in other ways and exhibit other characteristics.
It can be particularly difficult to sufficiently rectify the thickness non-uniformity of the useful layer 3 by the usual finishing techniques (etching, sacrificial oxidation, thermal smoothing treatment, polishing) in order to enable the required level of uniformity to be attained, when the latter is high.
It is possible to reduce the thickness non-uniformity of the useful layer 3 by trying to lower the temperature at which the initiation and the propagation of the fracture wave occur. This may be obtained, in a first approach, by lowering the temperature of the thermal embrittlement treatment step.
This approach, however, has the drawback of excessively lengthening the duration of the thermal embrittlement treatment, which is not favorable for the industrial exploitation of the method. In some cases, it turns out not to be possible to cause the initiation of the fracture, even for a very long treatment time, when the temperature of the thermal treatment is below a threshold temperature. This is notably the case for the fabrication of very thin SOI substrates, such as those previously mentioned.
Another approach, aimed at lowering the temperature at which the initiation and the propagation of the fracture wave occur, consists in causing this initiation by application of an external force, for example, a mechanical force, on the assembly to be fractured 5 situated at ambient temperature or at a moderate temperature, after the thermal treatment step, and without the latter having, in itself, caused this fracture.
However, this approach also has limitations. It requires the development of equipment dedicated to this mechanical fracture step, which can be complex and costly notably where the assembly to be fractured needs to be maintained at temperature.
In addition, this fracturing operation is likely to cause defects around the periphery of the useful layer 3 or of the carrier substrate 4, linked to the insertion of the mechanical element at the mounting interface of the assembly to be fractured 5.
Finally, this approach requires the parameters of the thermal embrittlement treatment step to be precisely controlled in order to bring the embrittlement plane into a sufficiently weakened state to enable the self-sustaining propagation of the fracture after mechanical initiation, without, however, exceeding a threshold beyond which this initiation occurs naturally in the course of the thermal treatment itself. This control is particularly tricky when the substrates are processed in batches, since each assembly of the batch to be fractured 5 can have a sensitivity to the thermal embrittlement treatment that is slightly different.